1. Field of the Invention
This invention relates to a semiconductor integrated circuit, and particularly to a gate array LSI.
2. Description of the Related Art
As a conventional gate array LSI, there is known one disclosed in Japanese Patent Application Laid-Open Publication No. 3-69163. The gate array LSI is one of a type that a plurality of basic cells each comprised of an NMOSFET having an N-type diffused region and a PMOSFET having a P-type diffused region are arranged in matrix form. Further, the gate array LSI is provided with a dedicated signal conductive pattern or conductor used for a clock signal and a test facilitation circuit. The dedicated signal conductor is used to suppress or control a reduction in performance of the clock signal and facilitate a test. A functional block such as a NAND circuit, an OR circuit or the like has been constructed by interconnecting the dedicated signal conductor, basic cells and a plurality of macrocells corresponding to wiring patterns with each other.
In the basic cells for the gate array LSI, basic cell patterns fabricated on a semiconductor substrate in advance and patterns for the signal conductor and a power conductive pattern or conductor have no symmetry in directions vertical and horizontal to the semiconductor substrate. It has thus been desirable to improve the efficiency of wiring the macrocells of the same patterns.